Tuesday, December 29, 2015

JBL CS200.1 CAR AMPLIFIER circuit diagram

JBL CS200.1

CONTROLS AND SETUP
SETTING THE CROSSOVER(S)
Determine your system plans and set the crossover mode switch accordingly. If your system design does not include a subwoofer with the CS50.4, set the crossover mode to FLAT and skip to “Setting Input Sensitivity.” Initially set the crossover frequency control midway. While listening to music, adjust the crossover for the least perceived distortion from the speakers, allowing them to reproduce as much bass as possible.
Systems using a separate subwoofer set the crossover mode to HP (high pass) for your full-range speakers. Adjust the crossover frequency to limit bass and provide increased system volume with less distortion.
For subwoofers, choose the highest frequency that removes vocal information from the sound of the subwoofer. If using the CS50.4 to drive a subwoofer(s), set the crossover mode to LP (low pass).
SETTING INPUT SENSITIVITY
1. Initially turn the INPUT LEVEL control(s) to minimum (counter clockwise).
2. Reconnect the (–) negative lead to the vehicle’s battery. Apply power to the audio system and play a dynamic music track.
3. On the source unit, increase the volume control to 3/4 volume. Slowly increase the INPUT LEVEL control(s) toward three o’clock until you hear slight distortion in the music. Then reduce the INPUT LEVEL slightly until distortion is no longer heard.
TROUBLESHOOTING
No audio (POWER LEDs are off)
Check voltages at amplifier terminals with VOM Make sure amplifier
No audio  (POWER LEDs are on)
Voltage more than 16V or less than 8.5V on BATT+ connection.
Make sure amplifier cooling is not blocked at mounting location; verify speaker-system impedance is within specified limits Check vehicle charging system.
No audio (POWER LEDs flash)
Voltage less than 9V on BATT+ connection DC voltage on amplifier output
Check vehicle charging system Amplifier may need service; see enclosed warranty card for service information.
ABOUT TL494 Driver ic
The TL494 device incorporates all the functions required in the construction of a pulse-width- modulation (PWM) control circuit on a single chip. Designed primarily for power-supply control, this device offers the flexibility to tailor the power-supply control circuitry to a specific application. The TL494 device contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC) comparator, a pulse-steering control flip-flop, a 5-V, 5%-precision regulator, and output-control circuits.
The error amplifiers exhibit a common-mode voltage range from –0.3 V to VCC – 2 V. The dead-time control comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common circuits in synchronous multiple-rail power supplies.
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The TL494 device provides for push-pull or single- ended output operation, which can be selected through the output-control function. The architecture of this device prohibits the possibility of either output being pulsed twice during push-pull operation. The TL494C device is characterized for operation from 0°C to 70°C. The TL494I device is characterized for operation from –40°C to 85°C.
Oscillator
The oscillator provides a positive sawtooth waveform to the dead-time and PWM comparators for comparison to the various control signals.
Dead-time Control
The dead-time control input provides control of the minimum dead time (off time). The output of the comparator inhibits switching transistors Q1 and Q2 when the voltage at the input is greater than the ramp voltage of the oscillator. An internal offset of 110 mV ensures a minimum dead time of
3% with the dead-time control input grounded. Applying a voltage to the dead-time control input can impose additional dead time. This provides a linear control of the dead time from its minimum of 3% to 100% as the input voltage is varied from 0 V to 3.3 V, respectively. With full-range control, the output can be controlled from external sources without disrupting the error amplifiers. The dead-time control input is a relatively high-impedance input (II < 10 μA) and should be used where additional control of the output duty cycle is required. However, for proper control, the input must be terminated. An open circuit is an undefined condition.
Comparator
The comparator is biased from the 5-V reference regulator. This provides isolation from the input supply for improved stability. The input of the comparator does not exhibit hysteresis, so protection against false triggering near the threshold must be provided. The comparator has a response time of 400 ns from either of the controlsignal inputs to the output transistors, with only 100 mV of overdrive. This ensures positive control of the output within one-half cycle for operation within the recommended 300-kHz range.
Pulse-Width Modulation (PWM)
The comparator also provides modulation control of the output pulse width. For this, the ramp voltage across timing capacitor CT is compared to the control signal present at the output of the error amplifiers. The timing capacitor input incorporates a series diode that is omitted from the control signal input. This requires the control signal (error amplifier output) to be
0.7 V greater than the voltage across CT to inhibit the output logic, and ensures maximum duty cycle operation without requiring the control voltage to sink to a true ground potential. The output pulse width varies from 97% of the period to 0 as the voltage present at the error amplifier output varies from 0.5 V to 3.5 V, respectively.
Error Amplifiers
Both high-gain error amplifiers receive their bias from the VI supply rail. This permits a common-mode input voltage range from –0.3 V to 2 V less than VI. Both amplifiers behave characteristically of a single-ended singlesupply amplifier, in that each output is active high only. This allows each amplifier to pull up independently for a decreasing output pulse-width demand. With both outputs ORed together at the inverting input node of the PWM comparator, the amplifier demanding the minimum pulse out dominates. The amplifier outputs are biased low by a current sink to provide maximum pulse width out when both amplifiers are biased off.
Output-Control Input
The output-control input determines whether the output transistors operate in parallel or push-pull. This input is the supply source for the pulse-steering flip-flop. The output-control input is asynchronous and has direct control over the output, independent of the oscillator or pulse-steering flip-flop. The input condition is intended to be a fixed condition that is defined by the application. For parallel operation, the output-control input must be grounded. This disables the pulse-steering flip-flop and inhibits its outputs. In this mode, the pulses seen at the output of the dead-time control/PWM comparator are transmitted by both output transistors in parallel. For pushpull operation, the output-control input must be connected to the internal 5-V reference regulator. Under thiscondition, each of the output transistors is enabled, alternately, by the pulse-steering flip-flop.
Output Transistors
Two output transistors are available on the TL494. Both transistors are configured as open collector/open emitter, and each is capable of sinking or sourcing up to 200 mA. The transistors have a saturation voltage of less than 1.3 V in the common-emitter configuration and less than 2.5 V in the emitter-follower configuration. The outputs are protected against excessive power dissipation to prevent damage, but do not employ sufficient current limiting to allow them to be operated as current-source outputs.
Device Functional Modes
When the OUTPUT CTRL pin is tied to ground, the TL494 is operating in single-ended or parallel mode. When the OUTPUT CTRL pin is tied to VREF, the TL494 is operating in normal push-pull operation.
SCHEMATIC DIAGRAM 
POWER AMPLIFIER 
POWER SUPPLY SECTION 
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