Monday, February 15, 2016

SANYO LCD-47S10-HD – Service mode – white balance adjustment – power supply circuit schematic diagram - FAN7602 - L6598 - UCC28019

Category: LCD Television Repair and Service 

Contents of this article 

  • Service mode access
  • White balance adjustment  
  • Power supply schematic 

SANYO LCD-47S10-HD

On-screen Service Menu System
1) How to enter the Service Menu
1. Press MENU button on SIDE controls, MENU will display.
2. Press and hold MENU button on SIDE controls and press “1” button on remote controls. SERVICE MENU will display
EXIT
Press the MENU button repeatedly or turn off the TV set by pressing the POWER ON/OFF button.
White Balance Adjustment
How to adjust White Balance Adjustment
1. Input white pattern to the composite input terminal
2. set the television to the flowing condition.
Picture mode: standard
Color temperature: normal
Pre:heading time : more than 10 minutes
3. enter to service mode and select WHITE BALANCE   with up or down button
Press lef or right button to enter the white balance adjustment, press corresponding number key to adjust RGB
3.After adjustment ,confirm white balance again by normal picture.
FAN7602 Current Mode PWM Controller
Description
The FAN7602 is a green current mode PWM controller. It is specially designed for off-line adapter application, DVDP, VCR, LCD monitor application, and auxiliary power supplies. The internal high-voltage start-up switch and the burstmode operation reduce the power loss in standby mode. Because of the internal start-up switch and the burst mode, it is possible to supply 0.5W load, limiting the input power to under 1W when the input line voltage is 265V AC. On no-load condition, the input power is under 0.3W. The maximum power can be limited constantly, regardless of the line voltage change, using the power limit function. The switching frequency is internally fixed at 65kHz and the frequency modulation technique reduces EMI. The FAN7602 includes various protections for the system reliability and the internal soft-start prevents the output voltage overshoot at start-up.
Pin configuration
1 LUVP Line Under-Voltage Protection Pin. This pin is used to protect the set when the input voltage is lower than the rated input voltage range.
2 Latch/Plimit Latch Protection and Power Limit Pin. When the pin voltage exceeds 4V, the latch protection works. The latch protection is reset when the VCC voltage is lower than 5V. For the power limit function, the Over-Current Protection (OCP) level decreases as the pin voltage increases.
3 CS/FB Current Sense and Feedback Pin. This pin is used to sense the MOSFET current for the current mode PWM and OCP. The output voltage feedback information and the current sense information are added using an external RC filter.
4 GND Ground Pin. This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power ground should be separated.
5 OUT Gate Drive Output Pin. This pin is an output pin to drive an external MOSFET. The peak sourcing current is 450mA and the peak sinking current is 600mA. For proper operation, the stray inductance in the gate driving path must be minimized.
6 V CC Supply Voltage Pin. IC operating current and MOSFET driving current are supplied using this pin.
7 NC No Connection.
8 Vstr Start-up Pin. This pin is used to supply IC operating current during IC start-up. After start-up, the internal JFET is turned off to reduce power loss.
L6598 High voltage resonant controller
Description
The L6598 device is manufactured with the BCD offline technology, able to ensure voltage ratings up to 600 V, making it perfectly suited for AC/DC adapters and wherever a resonant topology can be beneficial. The device is intended to drive two power MOSFETs, in the classical half bridge topology. A dedicated timing section allows the designer to set soft-start time, soft-start and minimum frequency. An error amplifier, together with the two enable inputs, are made available. In addition, the integrated bootstrap diode and the Zener clamping on low voltage supply, reduces to a minimum the external parts needed in the applications.
Pin configuration
1 CSS Soft-start timing capacitor
2 Rfstart Soft-start frequency setting - low impedance voltage source -see also Cf
3 Cf Oscillator frequency setting - see also Rfmin, Rfstart
4 Rfmin Minimum oscillation frequency setting - low impedance voltage source - see also Cf
5 OPout Sense op amp output - low impedance
6 OPon- Sense op amp inverting input -high impedance
7 OPon+ Sense op amp non inverting input - high impedance
8 EN1 Half bridge latched enable
9 EN2 Half bridge unlatched enable
10 GND Ground
11 LVG Low side driver output
12 Vs Supply voltage with internal Zener clamp
13 N.C. Not connected
14 OUT High side driver reference
15 HVG High side driver output
16 Vboot Bootstrapped supply voltage
UCC28019 PFC Controller
DESCRIPTION
The UCC28019 8-pin active Power Factor Correction (PFC) controller uses the boost topology operating in Continuous Conduction Mode (CCM). The controller is suitable for systems in the 100 W to >2 kW range over a wide-range universal ac line input. Startup current during under-voltage lockout is less than 200 µA. The user can control low power standby mode by pulling the VSENSE pin below 0.77 V. Low-distortion wave-shaping of the input current using average current mode control is achieved without input line sensing, reducing the Bill of Materials component count. Simple external networks allow for flexible compensation of the current and voltage control loops. The switching frequency is internally fixed and trimmed to better than 5% accuracy at 25°C. Fast 1.5-A gate peak current drives the external switch. Numerous system-level protection features include peak current limit, soft over-current detection, open-loop detection, input brown-out detection, output over-voltage protection/under-voltage detection, a no-power discharge path on VCOMP, and overload protection on ICOMP. Soft-Start limits boost current during start-up. A trimmed internal reference provides accurate protection thresholds and regulation set-point. An internal clamp limits the gate drive voltage to 12.5 V.
Pin configuration
GATE 8 - source capability. Output voltage is clamped at 12.5 V.
GND 1 Ground: Device ground reference.
ICOMP 2  - Current loop compensation: Transconductance current amplifier output. A capacitor connected to GND provides compensation and averaging of the current sense signal in the current control loop. The controller is disabled if the voltage on ICOMP is less than 0.6 V.
ISENSE 3  - Inductor current sense: An input for the voltage across the external current sense resistor, which represents the instantaneous current through the PFC boost inductor. This voltage is averaged to eliminate the effects of noise and ripple. Soft Over Current (SOC) limits the average inductor current. Cycle-by-cycle peak current limit (PCL) immediately shuts off the GATE drive if the peak-limit voltage is exceeded. Use a 220-Ω resistor between this pin and the current sense resistor to limit inrush-surge currents into this pin.
VCC 7  Device supply: External bias supply input. Under Voltage Lock Out (UVLO) disables the controller until VCC exceeds a turn-on threshold of 10.5 V. Operation continues until VCC falls below the turn-off (UVLO) threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 µF minimum value should be connected from VCC to GND as close to the device as possible for high frequency filtering of the VCC voltage.
VCOMP 5 -  Voltage loop compensation: Transconductance voltage error amplifier output. A resistor-capacitor network connected from this pin to GND provides compensation. VCOMP is held at GND until VCC, VINS, and VSENSE all exceed their threshold voltages. Once these conditions are satisfied, VCOMP is charged until the VSENSE voltage reaches 95% of its nominal regulation level. When the Enhanced Dynamic Response (EDR) is engaged, additional current is applied to VCOMP to reduce the charge time. EDR additional current is inhibited during soft-start. Soft-start is programmed by the capacitance on this pin.
VINS 4  - Input ac voltage sense: Input Brown Out Protection (IBOP) detects when the system ac-input voltage is above a user-defined normal operating level, or below a user-defined “brown-out” level. A filtered resistor-divider network connects from this pin to the rectified-mains node. At startup the controller is disabled until the VINS voltage exceeds a threshold of 1.5 V, initiating a soft-start. The controller is also disabled if VINS drops below the brown-out threshold of 0.8 V. Operation will not resume until both VINS and VSENSE voltages exceed their enable thresholds, initiating another soft-start.
VSENSE 6  - Output voltage sense: An external resistor-divider network connected from this pin to the PFC output voltage provides feedback sensing for output voltage regulation. A small capacitor from this pin to GND filters high-frequency noise. Standby disables the controller and discharges VCOMP when the voltage at VSENSE drops below the enable threshold of 0.8V. An internal 100nA current source pulls VSENSE to GND for Open-Loop Protection (OLP), including pin disconnection. Output over-voltage protection (OVP) disables the GATE output when VSENSE exceeds 105% of the reference voltage. Enhanced Dynamic Response (EDR) rapidly returns the output voltage to its normal regulation level when a system line or load step causes VSENSE to fall below 95% of the reference voltage
POWER SUPPLY SCHEMATICS 
ICS USED FAN7602 - L6598 - UCC28019
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