SHARP BLU RAY
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SHARP LC-42SB45U
SERVICE MODE AND POWER SUPPLY CIRCUIT
HOW TO ACTIVE FACTORY MODE
1. Press Nunber kyes “0- 6 - 2 - 5 - 9 - 6” + “Display” . Keep the display key pressed until the following display appears on the screen.
1. Press Nunber kyes “0- 6 - 2 - 5 - 9 - 6” + “Display” . Keep the display key pressed until the following display appears on the screen.
2. Choose “Factory” on the display and
press “ RIGHT ARROW BUTTON and select ”start now” and then press ENTER to activate the
factory mode.
3.In the factory setting press UP and DOWN button to select the item .
4.Choose Menu button to exit. or choose 0 in the
menu selection by up down key then press enter.
HOW TO RESET THE TV TO FACTORY DEFAULT
1.Enter to the factory ,then choose VIRGIN MODE .
1.Enter to the factory ,then choose VIRGIN MODE .
2.Select it ON By
pressing RIGT ARROW button.
3. Choose Menu button to exit. or choose 0 in the menu selection by up down key then press enter.
4. Power Off the TV.
4. Power Off the TV.
when you power ON the tv next time it will be at factory default setting .
SOFTWARE UPGRADE PROCEDURE
Environment Setup
Before you start to write the code, we suggest you setup the environment first. This chapter lists the setup requirements and guides you to setup and test your development environment.
Connect to ISP Board.
Use USB port connecting PC & MT537x Board via ISP board(Code number: 715G537XL2).
Environment Setup
Before you start to write the code, we suggest you setup the environment first. This chapter lists the setup requirements and guides you to setup and test your development environment.
Connect to ISP Board.
Use USB port connecting PC & MT537x Board via ISP board(Code number: 715G537XL2).
1. Unzip USB2COM Driver.zip to C:\
2. Unzip USB2COM Driver.zip to C:\
Use MTK_Tools to download .bin file. (Ex: F4_dbg_image.bin or F4_image.bin)
3. Make sure the Type “MTK538X” && “USB Baud Rate 115200” && Load the correct “bin” file. Load .bin file on the Linux system or on the local Windows file system(Ex: SHARP_ATSC_DLH_V0_34A_080714.bin) & Set Bridge & Auto Set Flash BaudRate
Use MTK_Tools to download .bin file. (Ex: F4_dbg_image.bin or F4_image.bin)
3. Make sure the Type “MTK538X” && “USB Baud Rate 115200” && Load the correct “bin” file. Load .bin file on the Linux system or on the local Windows file system(Ex: SHARP_ATSC_DLH_V0_34A_080714.bin) & Set Bridge & Auto Set Flash BaudRate
4. Set COM port resource that used by USB
Port.
5. Set Baud rate 115200 & High speed item
Enable. & MT538x.
6. Push “Upgrade” button. (Waiting for
“Finished!” message.) Press “確定” button
7. Mainboard Power Off - On.
MAJOR IC INFORMATION
MT5382 AR
The MediaTek MT5382AR consists of a
DTV front-end demodulator, a backend decoder and a TV controller and offers
high integration for advanced
applications. It combines a transport de-multiplexer, a high definition MPEG-2 video decoder, an AC3 audio decoder, an LVDS transmitter, and an
NTSC/PAL/SECAM TV decoder with a 3D comb filter. The MT5382AR enables consumer electronics manufactures to build high quality, low cost and feature-rich iDTVs.
World-Leading Audio/Video Technology: The MT5382AR family has built-in high resolution and high-quality audio codec. It includes MediaTek
MDDiTM de-interlace solution to generate very smooth picture quality for motions. A 3D comb filter added to the TV decoder recovers great detail for still
pictures.The special color processing technology provides natural, deep colors and true studio quality graphics.
Rich Features for High Value Products: The MT5382AR enables a true single-chip experience. It integrates high-quality HDMI1.3, high speed VGA
ADC,dual-channel LVDS, USB2.0 receiver and multi-media decoder.
Reliable Front-end Receiving Capability: Excellent adjacent and co-channel rejection capability grants customers never miss any wonderful stream. Professional error-concealment provides stable, smooth and mosaic-free video quality.
applications. It combines a transport de-multiplexer, a high definition MPEG-2 video decoder, an AC3 audio decoder, an LVDS transmitter, and an
NTSC/PAL/SECAM TV decoder with a 3D comb filter. The MT5382AR enables consumer electronics manufactures to build high quality, low cost and feature-rich iDTVs.
World-Leading Audio/Video Technology: The MT5382AR family has built-in high resolution and high-quality audio codec. It includes MediaTek
MDDiTM de-interlace solution to generate very smooth picture quality for motions. A 3D comb filter added to the TV decoder recovers great detail for still
pictures.The special color processing technology provides natural, deep colors and true studio quality graphics.
Rich Features for High Value Products: The MT5382AR enables a true single-chip experience. It integrates high-quality HDMI1.3, high speed VGA
ADC,dual-channel LVDS, USB2.0 receiver and multi-media decoder.
Reliable Front-end Receiving Capability: Excellent adjacent and co-channel rejection capability grants customers never miss any wonderful stream. Professional error-concealment provides stable, smooth and mosaic-free video quality.
LP2996MRX PSOP-8
The LP2996 linear regulator is designed to
meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device
contains a high-speed operational amplifier to provide excellent response to load transients. The
output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM
termination. The LP2996 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. An
additional feature found on the LP2996 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT
output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through
lower quiescent current.
L5985 VFQFPN8
The L5985 is a step down switching regulator
with 2.5A current limited embedded power MOSFET, so it is able to deliver up to
2A DC current to the load
depending on the application condition. The input voltage can range from 2.9V to 18V, while the output voltage can be set starting from 0.6V to VIN. Having a minimum input voltage of 2.9V, the device is suitable for buses staring from for 3.3V bus. Requiring a minimum set of external components, the device includes an internal 250KHz switching frequency oscillator that can be externally adjusted up to 1MHz. The QFN package with exposed pad allows reducing the RthJA down to approximately 60 Degree C/W.
depending on the application condition. The input voltage can range from 2.9V to 18V, while the output voltage can be set starting from 0.6V to VIN. Having a minimum input voltage of 2.9V, the device is suitable for buses staring from for 3.3V bus. Requiring a minimum set of external components, the device includes an internal 250KHz switching frequency oscillator that can be externally adjusted up to 1MHz. The QFN package with exposed pad allows reducing the RthJA down to approximately 60 Degree C/W.
HYB18TC256160BF-3S TFBGA-84-55
The 256-Mbit Double-Data-Rate-Two SDRAM
offers the following key features:
# 1.8 V ± 0.1 V Power Supply
# 1.8 V ± 0.1 V (SSTL_18) compatible I/O
# DRAM organizations with 4, 8 and 16 data in/outputs
# Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation
# Programmable CAS Latency: 3, 4, 5 and 6
# Programmable Burst Length: 4 and 8
# Differential clock inputs (CK and CK)
# Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write
# 1.8 V ± 0.1 V Power Supply
# 1.8 V ± 0.1 V (SSTL_18) compatible I/O
# DRAM organizations with 4, 8 and 16 data in/outputs
# Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation
# Programmable CAS Latency: 3, 4, 5 and 6
# Programmable Burst Length: 4 and 8
# Differential clock inputs (CK and CK)
# Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write
TDA8932B
The TDA8932B is a high efficiency class-D
amplifier with low power dissipation.
The continuous time output power is 2 ´ 15 W in stereo half-bridge application (RL = 4 W) or 1 ´ 30 W in mono full-bridge application (RL = 8 W). Due to
the low power dissipation the device can be used without any external heat sink when playing music. Due to the implementation of thermal foldback, even
for high supply voltages and/or lower load impedances, the device remains operating with considerable music output power without the need for an external heat sink.
The device has two full-differential inputs driving two independent outputs. It can be used
as mono full-bridge configuration (BTL) or as stereo half-bridge configuration (SE).
The continuous time output power is 2 ´ 15 W in stereo half-bridge application (RL = 4 W) or 1 ´ 30 W in mono full-bridge application (RL = 8 W). Due to
the low power dissipation the device can be used without any external heat sink when playing music. Due to the implementation of thermal foldback, even
for high supply voltages and/or lower load impedances, the device remains operating with considerable music output power without the need for an external heat sink.
The device has two full-differential inputs driving two independent outputs. It can be used
as mono full-bridge configuration (BTL) or as stereo half-bridge configuration (SE).
LD1117DT33TR
The LD1117 is a LOW DROP Voltage Regulator
able to provide up to 800mA of Output Current, available even in adjustable
version (Vref=1.25V).
Concerning fixed versions, are offered the following Output Voltages: 1.2V,1.8V,2.5V,2.85V, 3.0V 3.3V and 5.0V. The 2.85V type is ideal for
SCSI-2 lines active termination. The device is supplied in: SOT-223, DPAK, SO-8, TO-220 and TO-220FM. The SOT-223 and DPAK surface
mount packages optimize the thermal characteristics even offering a relevant space saving effect. High efficiency is assured by NPN
pass transistor. In fact in this case, unlike than PNP one, the Quiescent Current flows mostly into the load. Only a very common 10µF minimum
capacitor is needed for stability. On chip trimming allows the regulator to reach a very tight output voltage tolerance, within ± 1% at 25°C. The
ADJUSTABLE LD1117 is pin to pin compatible with the other standard. Adjustable voltage regulators maintaining the better performances in terms of Drop and Tolerance.
Concerning fixed versions, are offered the following Output Voltages: 1.2V,1.8V,2.5V,2.85V, 3.0V 3.3V and 5.0V. The 2.85V type is ideal for
SCSI-2 lines active termination. The device is supplied in: SOT-223, DPAK, SO-8, TO-220 and TO-220FM. The SOT-223 and DPAK surface
mount packages optimize the thermal characteristics even offering a relevant space saving effect. High efficiency is assured by NPN
pass transistor. In fact in this case, unlike than PNP one, the Quiescent Current flows mostly into the load. Only a very common 10µF minimum
capacitor is needed for stability. On chip trimming allows the regulator to reach a very tight output voltage tolerance, within ± 1% at 25°C. The
ADJUSTABLE LD1117 is pin to pin compatible with the other standard. Adjustable voltage regulators maintaining the better performances in terms of Drop and Tolerance.
LD1117DTTR
The LD1117 is a LOW DROP Voltage Regulator
able to provide up to 800mA of Output Current, available even in adjustable
version (Vref=1.25V).
Concerning fixed versions, are offered the following Output Voltages: 1.2V,1.8V,2.5V,2.85V, 3.0V 3.3V and 5.0V. The 2.85V type is ideal for
SCSI-2 lines active termination. The device is supplied in: SOT-223, DPAK, SO-8 and TO-220. The SOT-223 and DPAK surface mount packages optimize
the thermal characteristics even offering a relevant space saving effect. High efficiency is assured by NPN pass transistor. In fact in this case, unlike than
PNP one, the Quiescent Current flows mostly into the load. Only a very common 10µF minimum capacitor is needed for stability. On chip trimming allows
the regulator to reach a very tight output voltage tolerance, within ± 1% at 25°C. The ADJUSTABLE LD1117 is pin to pin compatible with the other
standard. Adjustable voltage regulators maintaining the better performances in terms of Drop and Tolerance.
Concerning fixed versions, are offered the following Output Voltages: 1.2V,1.8V,2.5V,2.85V, 3.0V 3.3V and 5.0V. The 2.85V type is ideal for
SCSI-2 lines active termination. The device is supplied in: SOT-223, DPAK, SO-8 and TO-220. The SOT-223 and DPAK surface mount packages optimize
the thermal characteristics even offering a relevant space saving effect. High efficiency is assured by NPN pass transistor. In fact in this case, unlike than
PNP one, the Quiescent Current flows mostly into the load. Only a very common 10µF minimum capacitor is needed for stability. On chip trimming allows
the regulator to reach a very tight output voltage tolerance, within ± 1% at 25°C. The ADJUSTABLE LD1117 is pin to pin compatible with the other
standard. Adjustable voltage regulators maintaining the better performances in terms of Drop and Tolerance.
LD39080PT
The LD39080 is a fast ultra low drop linear
regulator which operates from 2.5V to 6V input supply. A wide range of output
options are available. The
low drop voltage, low noise, and ultra low quiescent current make it suitable for low voltage microprocessor and memory applications. The device is
developed on a BiCMOS process which allows low quiescent current operation independently of output load current.
low drop voltage, low noise, and ultra low quiescent current make it suitable for low voltage microprocessor and memory applications. The device is
developed on a BiCMOS process which allows low quiescent current operation independently of output load current.
M24C02-WDW6P TSSOP8
These I2C-compatible electrically erasable
programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8
(M24C16, M24C08,
M24C04, M24C02 and M24C01).
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. ECOPACK packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
I²C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010)
in accordance with the I²C bus definition.
The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by
a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is
read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read
M24C04, M24C02 and M24C01).
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. ECOPACK packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
I²C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010)
in accordance with the I²C bus definition.
The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by
a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is
read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read
POWER SUPPLY CIRCUIT
CLICK ON THE IMAGE TO ZOOM IN
