Category: LED television Repair and Service
Contents of this article
- Power supply schematic digram
- BD9486 LED driver description
PHILIPS BA4AFSG02011
BD9486F LED Driver for large LCD
Description
BD9486F is a high efficiency driver for white LEDs and is designed for large LCDs. BD9486F has a boost DCDC converter that employs an array of LEDs as the light source.
BD9486F has some protect functions against fault conditions, such as over-voltage protection (OVP), over current limit protection of DCDC (OCP), LED OCP protection, and Over boost protection (FBMAX).
Therefore it is available for the fail-safe design over a wide range output voltage.
Features
# DCDC converter with current mode
# VOUT discharge function at shutdown
# LED protection circuit (Over boost protection, LED OCP protection)
# Over-voltage protection (OVP) for the output voltage Vout
# Adjustable soft start
# Adjustable oscillation frequency of DCDC
# Wide range of analog dimming 0.2V to 3.0V
# UVLO detection for the input voltage of the power stage
Applications
# TV, Computer Display, LCD Backlighting
BD9486F is a high efficiency driver for white LEDs and is designed for large LCDs. BD9486F has a boost DCDC converter that employs an array of LEDs as the light source.
BD9486F has some protect functions against fault conditions, such as over-voltage protection (OVP), over current limit protection of DCDC (OCP), LED OCP protection, and Over boost protection (FBMAX).
Therefore it is available for the fail-safe design over a wide range output voltage.
Features
# DCDC converter with current mode
# VOUT discharge function at shutdown
# LED protection circuit (Over boost protection, LED OCP protection)
# Over-voltage protection (OVP) for the output voltage Vout
# Adjustable soft start
# Adjustable oscillation frequency of DCDC
# Wide range of analog dimming 0.2V to 3.0V
# UVLO detection for the input voltage of the power stage
Applications
# TV, Computer Display, LCD Backlighting
Pin Function
No.
|
IN/OUT
|
Function
|
1
|
Out
|
5.0V
output voltage pin and shutdown timer pin
|
2
|
In
|
IC
ON/OFF pin
|
3
|
In
|
Over
voltage protection detection pin
|
4
|
In
|
Under
voltage lock out detection pin
|
5
|
Out
|
Slow
start setting pin
|
6
|
In
|
External
PWM dimming signal input pin
|
7
|
Out
|
Charge
timer for abnormal state
|
8
|
In
|
ADIM
signal input pin
|
9
|
Out
|
DC/DC
switching frequency setting pin
|
10
|
Out
|
Error
amplifier output pin
|
11
|
In
|
LED
current detection input pin
|
12
|
-
|
-
|
13
|
Out
|
Dimming
signal output for NMOS
|
14
|
Out
|
DC/DC
switching output pin
|
15
|
In
|
DC/DC
output current detect pin, OCP input pin
|
16
|
In
|
Power
supply pin
|
Pin Description
Pin 1: REG50
This is the 5.0V(typ.) output pin. Available current is 5mA (min). And this terminal is also used as timer for discharging DCDC output capacitor. Please refer to section“ 3.2.2 Shutdown Method and REG50 Capacitance Setting”, for detailed explanation.
Pin 1: REG50
This is the 5.0V(typ.) output pin. Available current is 5mA (min). And this terminal is also used as timer for discharging DCDC output capacitor. Please refer to section“ 3.2.2 Shutdown Method and REG50 Capacitance Setting”, for detailed explanation.
Pin
2: STB
This is the ON/OFF setting terminal of the IC. Input reset-signal to this terminal to reset IC from latch-off. At startup, internal bias starts at high level, and then PWM DCDC boost starts after PWM rise edge inputs.
Note: IC status (IC ON/OFF) transits depending on the voltage inputted to STB terminal. Avoid the use of intermediate level (from 0.8V to 2.0V). In order to discharge output voltage while STB=L and REG50UVLO=H, DIMOUT can assert High, depending on PWM logic. About discharge behavior at end, please refer to section “3.5.3 Timing Chart” or section “3.2.2 Shutdown Method and REG50 Capacitance Setting”.
Pin 3: OVP
The OVP terminal is the input for over-voltage protection. If OVP is more than 3.0V(typ), the over-voltage protection (OVP) will work. At the moment of these detections, it sets GATE=L, DIMOUT=L and starts to count up the abnormal interval. If OVP detection continued to count four GATE clocks, IC reaches latch off. (Please refer to “3.5.5 Timing Chart”) The OVP pin is high impedance, because the internal resistance is not connected to a certain bias. Even if OVP function is not used, pin bias is still required because the open connection of this pin is not a fixed potential. The setting example is separately described in the section ”3.2.7 OVP Setting”. As PWM=L interval, IC operates to keep the OVP pin voltage therefore the output voltage. Please refer the section “TBD the Retaining Function of The Output Voltage”.
Pin 4: UVLO
Under Voltage Lock Out pin is the input voltage of the power stage. , IC starts the boost operation if UVLO is more than 3.0V(typ) and stops if lower than 2.7V(typ). The UVLO pin is high impedance, because the internal resistance is not connected to a certain bias. Even if UVLO function is not used, pin bias is still required because the open connection of this pin is not a fixed potential.
The setting example is separately described in the section ”3.2.6 UVLO Setting”
This is the ON/OFF setting terminal of the IC. Input reset-signal to this terminal to reset IC from latch-off. At startup, internal bias starts at high level, and then PWM DCDC boost starts after PWM rise edge inputs.
Note: IC status (IC ON/OFF) transits depending on the voltage inputted to STB terminal. Avoid the use of intermediate level (from 0.8V to 2.0V). In order to discharge output voltage while STB=L and REG50UVLO=H, DIMOUT can assert High, depending on PWM logic. About discharge behavior at end, please refer to section “3.5.3 Timing Chart” or section “3.2.2 Shutdown Method and REG50 Capacitance Setting”.
Pin 3: OVP
The OVP terminal is the input for over-voltage protection. If OVP is more than 3.0V(typ), the over-voltage protection (OVP) will work. At the moment of these detections, it sets GATE=L, DIMOUT=L and starts to count up the abnormal interval. If OVP detection continued to count four GATE clocks, IC reaches latch off. (Please refer to “3.5.5 Timing Chart”) The OVP pin is high impedance, because the internal resistance is not connected to a certain bias. Even if OVP function is not used, pin bias is still required because the open connection of this pin is not a fixed potential. The setting example is separately described in the section ”3.2.7 OVP Setting”. As PWM=L interval, IC operates to keep the OVP pin voltage therefore the output voltage. Please refer the section “TBD the Retaining Function of The Output Voltage”.
Pin 4: UVLO
Under Voltage Lock Out pin is the input voltage of the power stage. , IC starts the boost operation if UVLO is more than 3.0V(typ) and stops if lower than 2.7V(typ). The UVLO pin is high impedance, because the internal resistance is not connected to a certain bias. Even if UVLO function is not used, pin bias is still required because the open connection of this pin is not a fixed potential.
The setting example is separately described in the section ”3.2.6 UVLO Setting”
Pin 5: SS
This is the pin which sets the soft start interval of DC/DC converter. It performs the constant current charge of 3.0 μA to external capacitance Css. The switching duty of GATE output will be limited during 0V to 3.7V of the SS voltage.
This is the pin which sets the soft start interval of DC/DC converter. It performs the constant current charge of 3.0 μA to external capacitance Css. The switching duty of GATE output will be limited during 0V to 3.7V of the SS voltage.
Pin 6: PWM
This is the PWM dimming signal input terminal
This is the PWM dimming signal input terminal
PWM=H PWM=1.5V to 18.0V
PWM=L PWM=‐0.3V to 0.8V
PWM=L PWM=‐0.3V to 0.8V
Pin 7: CP
Timer pin for counting the abnormal state of the over boost protection (FBMAX). If the abnormal state is detected, the CP pin starts charging the external capacitance by 3μA. As the CP voltage reaches 3.0V, IC will be latched off. (GATE=L, DIMOUT=L)..
Pin 8: ADIM
This is the input pin for analog dimming signal. The ISENSE feedback point is set as 1/3 of this pin bias. If more than 3.0V is input, ISENSE feedback voltage is clamped to limit to flow LED large current. In this condition, the input current is caused.
Timer pin for counting the abnormal state of the over boost protection (FBMAX). If the abnormal state is detected, the CP pin starts charging the external capacitance by 3μA. As the CP voltage reaches 3.0V, IC will be latched off. (GATE=L, DIMOUT=L)..
Pin 8: ADIM
This is the input pin for analog dimming signal. The ISENSE feedback point is set as 1/3 of this pin bias. If more than 3.0V is input, ISENSE feedback voltage is clamped to limit to flow LED large current. In this condition, the input current is caused.
Pin 9: RT
This is the DC/DC switching frequency setting pin. DCDC frequency is decided by connected resistor.
This is the DC/DC switching frequency setting pin. DCDC frequency is decided by connected resistor.
Pin 10: FB
This is the output terminal of error amplifier.
FB pin rises with the same slope as the SS pin during the soft-start period.
This is the output terminal of error amplifier.
FB pin rises with the same slope as the SS pin during the soft-start period.
Pin 11: ISENSE
This is the input terminal for the current detection. Error amplifier compares the lower one among 1/3 of the voltage terminal ADIM analog dimming and 1.0V(typ). And it detects abnormal LED overcurrent at ISENSE=3.0V(typ) over. If GATE terminal continues during four CLKs (equivalent to 40μs at fosc = 100kHz), it becomes latch-off.
This is the input terminal for the current detection. Error amplifier compares the lower one among 1/3 of the voltage terminal ADIM analog dimming and 1.0V(typ). And it detects abnormal LED overcurrent at ISENSE=3.0V(typ) over. If GATE terminal continues during four CLKs (equivalent to 40μs at fosc = 100kHz), it becomes latch-off.
Pin 12: GND
This is the GND pin of the IC.
This is the GND pin of the IC.
Pin 13: DIMOUT
This is the output pin for external dimming NMOS. The table below shows the rough output logic of each operation state, and the output H level is VCC. Please refer to “3.5 Timing Chart” for detailed explanations, because DIMOUT logic has an exceptional behavior.
This is the output pin for external dimming NMOS. The table below shows the rough output logic of each operation state, and the output H level is VCC. Please refer to “3.5 Timing Chart” for detailed explanations, because DIMOUT logic has an exceptional behavior.
Pin 14: GATE
This is the output terminal for driving the gate of the boost MOSFET. The high level is VCC. Frequency can be set by the resistor connected to RT. Refer to <RT> pin description for the frequency setting.
This is the output terminal for driving the gate of the boost MOSFET. The high level is VCC. Frequency can be set by the resistor connected to RT. Refer to <RT> pin description for the frequency setting.
Pin 15: CS
The CS pin has two functions.
1. DC / DC current mode Feedback terminal
The inductor current is converted to the CS pin voltage by the sense resistor RCS. This voltage compared to the voltage set by error amplifier controls the output pulse.
2. Inductor current limit (OCP) terminal
The CS terminal also has an over current protection (OCP). If the voltage is more than 0.4V(typ.), the switching operation will be stopped compulsorily. And the next boost pulse will be restarted to normal frequency. In addition, the CS voltage is more than 1.0V(typ.) during four GATE clocks, IC will be latch off. As above OCP operation, if the current continues to flow nevertheless GATE=L because of the destruction of the boost MOS, IC will stops the operation completely
The CS pin has two functions.
1. DC / DC current mode Feedback terminal
The inductor current is converted to the CS pin voltage by the sense resistor RCS. This voltage compared to the voltage set by error amplifier controls the output pulse.
2. Inductor current limit (OCP) terminal
The CS terminal also has an over current protection (OCP). If the voltage is more than 0.4V(typ.), the switching operation will be stopped compulsorily. And the next boost pulse will be restarted to normal frequency. In addition, the CS voltage is more than 1.0V(typ.) during four GATE clocks, IC will be latch off. As above OCP operation, if the current continues to flow nevertheless GATE=L because of the destruction of the boost MOS, IC will stops the operation completely
Pin 16: VCC
This is the power supply pin of the IC. Input range is from 9V to 18V.
The operation starts at more than 7.5V(typ) and shuts down at less than 7.2V(typ)
This is the power supply pin of the IC. Input range is from 9V to 18V.
The operation starts at more than 7.5V(typ) and shuts down at less than 7.2V(typ)
POWER SUPPLY CIRCUIT
CLICK ON THE IMAGE TO ZOOM IN
